1. Field of the Invention
The present invention relates to testing a device under test.
2. Discussion of the Background Art
A source synchronous input/output (I/O) interface is designed to handle data transfer using a local clock domain. I.e., the timing of the data bits being transferred from a data transmitting device to a data receiving device is referenced to the local clock of that device. In other words, the timing of the data is not referenced to an absolute timing scheme as provided by a system clock of a data receiving system, which has both devices as constituent parts. Thus, a bit stream corresponding to a clock information accompanies one or more parallel bit streams of data. At the receiver's side these data bits may then be buffered and linked to that clock information in order to recover and retrieve the information in an appropriate timing scheme.
A reason for implementing a source synchronous interface is that with increasing throughput of data in high speed computational systems, which recently crossed the barrier of 1 Gigabit per second, limited signal propagation speed along interconnects in those systems becomes a dominant factor in respect of the setting of timing schemes in each device of such a system. Due to differing interconnect lengths, if measured from a common clock device, transmitting and receiving devices which communicate via an interface may acquire deviating timing information from the system clock, that is provided with a constant or even variable skew.
Recent source synchronous I/O bus architectures use the forwarded local clock information just as a frequency reference and adjust the phase for each of the parallel bit lines. The static skew of the individual data bit lines is adjusted during link up using dedicated training sequences.
Further, these interfaces are capable of handling common mode phase variations of the clock and data information, i.e., jitter. Source synchronous operation of the communication is thereby enabled despite the presence of thermal drifts and/or supply voltage variations. This means that the original purpose of mainly covering a static skew difference between system clock and local I/O data is extended to also cover dynamic clock drifts and higher frequency common mode jitter of the local I/O interface clock and its associated data.
In order to ensure a defined functional operation of a device, such device needs to be tested along with the core logic of such device. Such a test is usually performed using Automatic Test Equipment (ATE). Thereby, defined sequences of data bits are input as a stimulus signal to a device under test (DUT), which comprises, e.g., a data transmitting or receiving portion of a source synchronous interface. Having performed logical operations according to a dedicated test program, the data being processed are transmitted back to the ATE in response to the input stimulus signal via the source synchronous interface, i.e. data bits as well as its associated local clock information.
While jitter and drift in a source synchronous interface may be appropriately handled in the case of a computational system comprising, e.g., two communicating chips, common ATE's testing the interface of one of the chips use fixed strobes to validate the data and clock information. Common mode jitter or drift then disadvantageously tend to close a data eye of a transferred bit more rapidly than in the case of the two chips.
One solution is to provide the ATE with a receiving portion of a source synchronous interface, such that the DUT could be tested under similar conditions as during operation in the target system. However, different propagation delays for the spatially distributed I/O pins of the ATE have to be taken into account when designing the test equipment.